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Mobiprep has created last-minute notes for all topics of Computer networks to help you with the revision of concepts for your university examinations. So let’s get started with the lecture notes on Computer networks.
Our team has curated a list of the most important questions asked in universities such as DU, DTU, VIT, SRM, IP, Pune University, Manipal University, and many more. The questions are created from the previous year's question papers of colleges and universities.
Machine Instruction Set
Question 1) Explain various addressing modes used in computer architecture?
Answer) Addressing modes specify the rules of interpreting or modifying the address field of the instruction. Addressing modes provide versatility to the programmer for example pointers to memory, counters for loop control, indexing of data, program relocation etc.
Implied Mode:
This mode does NOT require the address field. The operand is specified “implicitly in the definition of the instruction”.
Example:
“Complement AC i.e. CMA” “Clear AC” “Increment AC i.e. INC/DEC” are implied as the operand is available in AC.
Mostly all registers reference instructions that use an accumulator are implied-mode instructions. Also, zero-address instructions in stack organization are implied mode instructions because the operand is implied on top of the stack.
Immediate Mode:
Here the operand is specified in the instruction itself, that is, immediate mode instructions have operand field instead of (in place of) an address field.
Example:
ADI 45 => Add immediately 45 to AC and store the result in AC.
MOV AL, 64H => Immediate 64 hexadecimal data transfer to AL.
The above two addressing modes require no address fields.
This does not require any reference to memory location BUT operand (its value) is itself available as an address.
Direct Address Mode:
In this mode the effective address is equal to the address part of the instruction. Here the operand resides in memory we directly get the address of the operand from the address field of the instruction.
Example: MOV AL, [0400H].
=> Here operand resides directly at memory address 0400H
The mode bit is 0 for a direct address and 1 for an indirect address
Indirect Address Mode:
The indirect address instruction needs two references to memory to fetch an operand. The first reference is needed to read the address of the operand; the second is for the operand itself.
Example:
1 | ADD | 300 |
25
Here 1 is mode bit and as mode bit value is 1 it is an indirect addressing mode
Add is the instruction and the operand are to be found at memory location 300
1150 |
300
So, the operand to be added is 1150.
Register Direct Addressing Mode:
In this addressing mode the operand is contained in a register set. The address field of the instruction refers to a CPU register that contains the operand. No reference to memory is required to fetch the operand.
Example
ADD R will increment the value stored in the accumulator by the content of register R.
AC ← AC + [R]
Register Indirect Mode:
Here the register field from the instruction specifies the address of the operand in the memory. That is the register contains the memory address rather than the operand itself. The advantage of using this mode is that a smaller number of bits is required in the instruction field to address a register rather than addressing the memory.
Example: MOV AX, [BX]
=> Go to the address stored in BX and move the content from there to AX.
Auto Increment Mode or Auto Decrement Mode:
This is similar to register increment mode except that the register is incremented or decremented after (or before) its value is used to access memory.
2 forms post and pre: -
Mov R1, (R2) + -> post increment
Mov R1, +(R2) -> pre increment
Mov R1, (R2)- -> post decrement
Mov R1, -(R2) ->pre decrement
Relative Address Mode:
Here the content of the program counter is added to the address part of the instruction to obtain the effective address.
Example:
Say PC = 725 and address part of the instruction = 24. Now when this instruction is fetched the PC is incremented to 726. The effective address is now computed as 726 + 24 = 750. This is 24 memory locations forward from the address of the next instruction.
Index Addressing Mode:
Here the content of the index register is added to the address part of the instruction to obtain an effective address. Index address is mostly used with arrays.
Effective Address= Content of Index Register + Address part of the instruction
Base Register Addressing Mode:
Here the content of the base register is added to the address part of the instruction to obtain an effective address. This is the same as index addressing mode but the value and name of the register is different. This mode is used to facilitate the relocation of programs in the memory generally used in dynamic memory allocation.
Numerical Example of addressing modes:
In the following example the instruction is of 2 words.
The value of PC = 20 therefore we will fetch instruction from 20.
And the two words instructions can be located at address 20 and 21. •
The opcode is “Load to AC” and the operand is equal to 50. •
Also, the content of Processor register (R1) is equal to 40 and content of Index register (XR) is equal to 10.
Now AC receives the operand after instruction is executed and we will calculate the effective address (EA) part of the instruction.
Direct Address: Here the EA is the address part of the instruction and is 50. The operand loaded from memory is 80.
Immediate Address: Here the operand is the second word of the instruction instead of EA. Therefore 50 is loaded into AC (EA = 21).
Indirect Address: Here the EA is stored at location 50 and therefore EA is 80. The operand loaded from memory is 30.
Relative Mode Address: Here the EA is 50 + 22 (value of PC) = 72. The operand loaded from memory is 35.
Index Mode Address: Here the EA is 50 + 10 (value of XR) = 60. The operand loaded from memory is 90.
Register Mode Address: Here the EA is the content of the register and 40 is loaded into AC. There is no EA in this case.
Register Indirect Address: Here the EA is the address part of the register and is 40. The operand loaded from memory is 70.
Autoincrement Address: It is same as register indirect mode except the R1 is incremented to 41 AFTER the execution of the instruction.
Auto Decrement Address: Here the value of R1 is decremented BEFORE (PRIOR) to the execution of the instruction. The operand loaded into AC is now 45.
Question 2) What are the various modes of data transfer between computer and external devices?
Answer) Data transfer between the computer and external device may be handled by one of the three possible modes:
Programmed I/O.
Interrupt-initiated I/O
Direct Memory Access (DMA)
Programmed I/O
Each Data transfer is initiated by instructions in a program (Transfer bet. CPU & I/O device). I/O instructions are executed according to operations written in a program. The I/O instruction transfers from and to CPU registers. A memory load instruction used to load its memory. Another instruction used to verify data and count the number of words transferred. Constant I/O monitoring is required by the CPU. The CPU stays in a program loop until the I/O unit indicates data ready. This is time Consuming and wastes CPU time.
I/O device and Interface use handshaking for data transfer. Once data available on Data Register Interface sets flag bit (F) indicating data availability. Interface do not reset data accepted line until CPU reads data and clear the flag
CPU needs 3 instruction for each byte transfer
Read the status register
Check the flag bit
Read data register when data available
Transfer can be done in blocks for efficiency
Interrupt-initiated I/O
In this method an interrupt facility an interrupt command is used to inform the device about the start and end of transfer. In the meantime, the CPU executes another program. When the interface determines that the device is ready for data transfer it generates an Interrupt Request and sends it to the computer.
When the CPU receives such a signal, it temporarily stops the execution of the program and branches to a service program to process the I/O transfer. The CPU gets deviated from the current program and takes care of data transfer. It saves the return address from program counter to stack and then control branches to service routing
After completing I/O transfer it returns back to previous program
There are two ways of choosing the branch address:
Vectored Interrupt
Non-vectored Interrupt
Vectored Interrupt: Here the source which generated Interrupt supplies the Branch Information to the CPU. Also called INTERRUPT VECTOR.
Non-vectored Interrupt: Here branch address is assigned to a fixed location in memory.
Direct Memory Access (DMA)
CPU limits the data transfer speed for fast I/O devices. DMA removes CPU and allows peripherals to handle memory bus. DMA directly transfers data bet. I/O device and Memory. During the transfer the CPU does not have the control over the bus. CPU idling the bus can be done through the control signals “Bus Request” & “Bus Grant”
DMA controller enables BR,
then CPU finishes current operation and puts its address and data buses in high impedance state
CPU sets BG line (to inform DMA busses are in High Impedance)
DMA transfers data and resets BR for the CPU to use the memory bus by the Interrupt.
DMA data transfer can either happen as – Burst transfer or – Cycle stealing
Question 3) What is an assembler?
Answer) An assembler is a program that accepts a symbolic language program and produces its binary machine language equivalent. The input symbolic program is called the source program and the resulting binary program is called the object program. The assembler is a program that operates on character strings and produces an equivalent binary interpretation.
Question 4) What is the four steps approach required to develop a design specification for an assembler?
Answer) There are four steps to develop a design specification for an assembler.
Identify the information necessary to perform a task.
Design a suitable data structure to record the information.
Determine the processing necessary to obtain and maintain the information.
Determine the processing necessary to perform the task.
Question 5) What do you mean by the term Instruction format?
Answer) Instruction Format (IF) is the function of the Control Unit within the CPU to interpret each Instruction Code & provide the necessary control function needed to process the instruction.
Format of an Instruction represents/symbolizes the bits as it appears in memory or Control Register.
Most Common Instruction Fields:
Label, Opcode, Operands, Comment
OP-code field - specifies the operation to be performed & can be ADD, SUBSTRACT, COMPLEMENT, SHIFT Etc.
Address field - designates memory address(s) or a processor register(s)
Labels and comments are optional fields.
Mode field - specifies the way the operand or the effective address is determined. The number of address fields in the instruction format depends on the internal organization of CPU
The number of address fields in the instruction format depends on the internal organization of CPU
Question 6) Using zero, one, two and three address instruction solve the arithmetic expression X=(A*B) +(C*D).
Answer) A, B, C, D = Operands are in these memory addresses. X = Result is stored at memory address X ADD, SUB, MUL, DIV = Arithmetic Operations LOAD, STORE = To transfers to and from memory and AC register MOV = Transfer-type operation.
Three-Address Instructions:
X = (A + B) * (C + D)
ADD R1, A, B
ADD R2, C, D
MUL X, R1, R2
Two-Address Instructions:
X = (A + B) * (C + D)
MOV R1, A
ADD R1, B
MOV R2, C
ADD R2, D
MUL R1, R2
MOV X, R1
One-Address Instructions:
X = (A + B) * (C + D):
LOAD A
ADD B
STORE T
LOAD C
ADD D
MUL T
STORE X
Zero-Address Instructions:
X = (A + B) * (C + D):
PUSH A
PUSH B
ADD
PUSH C
PUSH D
ADD
MUL
POP X
Question 7) What is RPN? Evaluate the following using RPN notation:
(A-B) *[C/(D+E) +F]
Answer) RPN stands for reverse polish notation and is also known as postfix expression. This expression avoids use of brackets to define priorities while dealing with multiple operators and operands.
Priority order:
1 ()
2*, /
3 +, -
Rules:
R1: No two operators of same priority can stay in the stack together
R2: If there is any situation where there is (operator/pair of operators) so pop the brackets and element inside it and add that element in postfix expression.
R3: A lower priority operator can’t be pushed over in the stack over a higher priority operator.
Now from the expression take one element at a time and if it is an operator then add in stack else add in postfix expression. Our ultimate goal is to make the stack empty.
(A-B) *[C/(D+E) +F]
Symbol | Stack | Postfix |
( | ( | |
A | | A |
- | (- | |
B | (- | AB |
) | (-) | AB |
Here we can see Rule R2 can be applied. So, we will pop the operand within the bracket as well as bracket and add the operant to the postfix expression.
) | | AB- |
* | * | AB- |
[ | *[ | AB- |
C | *[ | AB-C |
/ | *[/ | AB-C |
( | *[/( | AB-C |
D | *[/( | AB-CD |
+ | *[/(+ | AB-CD |
E | *[/(+ | AB-CDE |
) | *[/(+) | AB-CDE |
Applying Rule R2 again
) | *[/ | AB-CDE+ |
+ | *[/+ | AB-CDE+ |
F | *[/+ | AB-CDE+F |
] | *[/+] | AB-CDE+F |
Applying rule R2 again
] | * | AB-CDE+F+/ |
| | AB-CDE+F+/* |
| | |
Question 8) Evaluate the assembly language representation of,
X = (A+B * C) / (D-E), Using 0,1,2 and 3- address instruction length.
Answer) 3 addressing mode.
X = (A+B * C) / (D-E)
ADD R1, A, B
MUL R2, R1, C
SUB R3, D, E
DIV X, R2, R3
2 addressing mode
X = (A+B * C) / (D-E)
MOV R1, A
ADD R1, B
MUL R1, C
MOV R2, D
SUB R2, E
DIV R1, R2
MOV X, R1
1 addressing mode
LOAD D
SUB E
STORE M
LOAD A
ADD B
MUL C
DIV M
STORE X
0 addressing mode
PUSH C
PUSH D
SUB
PUSH A
PUSH B
ADD
PUSH C
MUL
DIV
POP X
Question 9) What is the difference between RISC and CISC?
Answer) RISC
A reduced instruction set computer is a computer that only uses simple commands that can be divided into several instructions that achieve low-level operation within a single CLK cycle, as its name proposes “Reduced Instruction Set
CISC
A complex instruction set computer is a computer where single instructions can perform numerous low-level operations like a load from memory, an arithmetic operation, and a memory store or are accomplished by multi-step processes or addressing modes in single instructions, as its name proposes “Complex Instruction Set”.
RISC | CISC |
Performance is optimized with more focus on software | Performance is optimized with more focus on hardware. |
Multiple register sets are present | Only has a single register set |
It has no memory unit and uses separate hardware to implement instructions. | It has a memory unit to implement complex instructions. |
Execution time is very less | Execution time is very high |
RISC processors are highly pipelined | They are normally not pipelined or less pipelined |
The decoding of instructions is simple. | Decoding of instructions is complex |
RISC architecture is used in high-end applications such as video processing, telecommunications, and image processing. | ISC architecture is used in low-end applications such as security systems, home automation, etc. |
Question 10) Enlist the significance of various registers present in Von Neuman architecture?
Answer) Unlike Harvard architecture in Von Neumann architecture both data and program are stored in the same place. So, the same mechanism is used to fetch data as well as program.
Various registers are present in Von Neumann architecture such as:
MBR: Memory Buffer Register- It contains the word to be stored in memory or just received from memory.
MAR: Memory Address Register- It specifies the address in memory of the word to be stored or retrieved.
IR: Instruction Register- It contains the 8-bit opcode currently being executed.
IBR: Instruction Buffer Register-It temporary store for RHS instruction from word in memory.
PC: Program Counter -It stores the address of next instruction-pair to fetch from memory.
AC: Accumulator & MQ- Multiplier quotient - holds operands and results of ALU ops.