Mobiprep has created last-minute notes for all topics of operating system to help you with the revision of concepts for your university examinations. So let’s get started with the lecture notes on Operating System (OS).
Our team has curated a list of the most important questions asked in universities such as DU, DTU, VIT, SRM, IP, Pune University, Manipal University, and many more. The questions are created from the previous year's question papers of colleges and universities.
Question- 1) What does the processor talk to the I/O device?
Answer: The old processors accessed the I/O devices using special I/O instructions. But, today’s processors communicate with the I/O devices via bus. I/O devices are accessed through memory mapped addresses.
There are three methods with which the I/O devices can be accessed by the processor. They are:
Programmed I/O- In programmed I/O, special I/O instructions are used to communicate with the I/O device
Interrupt driven I/O- Here, the I/O device sends an interrupt signal when it wants to communicate with the processor. When an interrupt occurs, the processor executes the interrupt service routine
Direct Memory Access- In this method, the data is transferred from the memory to the I/O device without the involvement of the CPU. This method is very efficient than the other two methods.
Question- 2) What is DMA?
Answer: Direct Memory Access allows the computer to transfer the data directly from the main memory to the I/O device and vice versa. The CPU (or processor) is not involved in this transaction. The DMA is an efficient method because it improves the efficiency of the processor. It speeds up the overall operation of the computer.
Question- 3) Give a description about Device Drivers?
Answer: Device drivers help the external I/O device to communicate with the Operating System. Without the device drivers, the interaction between the processor and the I/O devices is impossible. The device driver is a set of files which are hardware specific. The device drivers are needed when the features of the I/O device are not known to the computer.
Question- 4) What is the Life Cycle of an I/O request?
Answer: The following flow chart explains the life cycle of an I/O request:
When an I/O request occurs, the current process is blocked if the request is appropriate. Then, the request is processed. Once the I/O operation is completed, the control is transferred to the process, and the output of the I/O operation is returned.
Question- 5) What do you understand by Synchronous and Asynchronous I/O System?
Synchronous I/O system
In a synchronous I/O system, the I/O operations block the current process that is executed by the CPU. Here, the I/O operations are blocking. Synchronous I/O systems can perform either read operation or write operation at a time.
Asynchronous I/O system
In an asynchronous I/O system, the I/O operation and the user processes are executed simultaneously. Many simultaneous read/write operations are allowed. Here, the I/O operations are non-blocking. This system starts the execution of another process before completing the I/O operation. Such systems are more complex and less secure.
Question- 6) What are the Blocking and Non-Blocking input output?
In a blocking IO, the control is not returned to the process thread until the I/O operation is complete. Blocking IO is used in cases in which the process utterly needs the data from the I/O operation, and the process cannot be executed further until the I/O operation is over.
In a non-blocking I/O, the call is returned to the thread before the completion of the I/O operation. After the completion of the I/O call, the resulting data is returned to the corresponding application.
Question- 7) What are the characteristics of I/O Devices?
Answer: The following are the characteristics of an I/O device
An I/O device enables the users to communicate with the computer
The I/O devices can send data to the computer and receive data from the computer
The I/O devices require corresponding device drivers to interact with the CPU
The I/O devices can directly communicate with the memory through the DMA controller.
When an I/O device wants to interact with the CPU, it generates an interrupt signal.
Question- 8) Write about the Kernel I/O subsystem.
Answer: The kernel provides the following services to the I/O devices:
Scheduling refers to the order in which the I/O requests are processed. This order is decided by the priority of the I/O devices.
Caching helps in storage of data in a memory location which can be accessed by the processor faster than the other memory locations. The cache memory stores the duplicate copy of the data.
Buffer stores the data to be transferred between the devices temporarily.
A spool is a buffer which is similar to a queue. Spooling is the process in which the data is stored temporarily in a queue until the processor executes it.
Any error that occurs during an I/O operation is handled by the kernel.
The kernel provides exclusive access to an I/O device. The system calls are used for allocation and de-allocation of the device.
The I/O operation is considered as a privileged to prevent the usage of illegal I/O instructions by the user.
Question- 9) What are the different modes of Interrupt? How is polling achieved?
Answer: The two modes of interrupt are:
Maskable interrupt- Maskable interrupts are the interrupt that can be disabled by the CPU. Usually, lower priority interrupts are maskable. These interrupts are masked, and executed after the execution of the current process.
Non-maskable interrupt- Non-maskable interrupts are the interrupts that cannot be disabled by the CPU. These are higher priority interrupts. The current process being executed is stopped and the interrupt is handled.
When more than one interrupts occur at a time, the order in which the interrupts have to be serviced is determined the ISR. Polling method orders the interrupts according to their priority. The interrupts with the highest priority is handled first.
Question- 10) Explain the difference between an internal interrupt and software interrupt.
Question- 11) How is an interrupt enabled and detected?
Answer: A processor enables an interrupt by stopping the execution of the current process. The address of the current instruction is stored in the stack and the interrupt is handled by the Interrupt Service Routine.
The interrupt input is sampled during each instruction cycle. If the processor detects any interrupt requests during sampling, the processor immediately services the interrupt.
Question- 12) Explain the concepts of spooling.
Answer: SPOOL 🡪 Simultaneous Peripheral Operations On-Line
Spooling is the process in which the data is stored temporarily in a queue until the processor executes it. Spooling is used when the external peripheral devices communicate with the processor. The I/O devices are much slower than the processor. Spooling is used to synchronize the speeds of both the peripheral device and the processor.
The spool is similar to a queue. It accumulates various data from the I/O devices until they are executed by the processor. FIFO order is maintained while processing the spool. i.e. the first instruction in the spool is executed first by the processor.
Question- 13) Explain the architecture of DMA controller in detail.
Answer: The DMA controller is a device which controls the direct transfer of data between the I/O device and the memory without the involvement of the CPU. It improves the performance of the CPU by not keeping the CPU busy in transferring data between the I/O device and the memory.
The block diagram of the DMA Controller is given below:
Working of the DMA controller
The I/O device sends a request (DRQ Request) to the DMA controller, when the data has to be transferred between the I/O device and the memory. On receiving the request, the DMA controller sends the HOLD signal (HRQ Request) to the CPU, and waits for the HLDA signal from the CPU. Once the DMA controller receives the HLDA signal, it gets the control over the system buses. Now, the system buses are freed from the CPU.
When the write operation has to be performed by the peripheral device, it sends the MEMW and IOR signals. When the DMA controller receives the IOR signal, it loads the data on the data bus.
Once the data transfer is over, the control is returned back to the CPU. The switch position is shifted from Y to X. The CPU takes complete control of the system buses.